This invention pertains in general to memory systems and, more particularly, to a data protected memory system.
Currently available Memory systems are typically interfaced with a microprocessor core, which microprocessor core is operable to access any and all locations in the memory by generating an appropriate address. The processor requires access to the memory in order to both execute instructions and also read data from an address location or write data thereto.
In some situations, certain instructions are proprietary in nature and it is the desire of a manufacturer to protect that code. It is not the execution of the code that is to be protected but, rather, the ability of a user to gain access to the code, i.e., download the code, for reverse engineering thereof to determine the functionality that is embedded within the code. In systems that have provided this protected memory to prevent access to data or programs stored in the memory, circuitry is provided for monitoring the contents of the Program Counter and generating an inhibit signal whenever the Program Counter is at a certain value. This inhibit signal inhibits access to certain portions of the memory.
The invention disclosed and claimed herein comprises, in one aspect thereof, a protected memory. The protected memory includes an address input and a memory space of addressable locations having a restricted area and a user area. Addressing one of a the addressable locations therein results in the output of information therefrom in response to the receipt of an associated address on the address input. A logic device is provided for determining if a received address on the address input corresponds to an attempt to access an addressable location in the restricted space for output of information therefrom as the result of execution of a program instruction from the user area by an external processor. An inhibit device is provided for inhibiting access to the addressable location if a positive determination is made by the logic device.